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Open-source, low-cost 10.5 GHz PLFM phased array RADAR system

PLSQL 109.4 MB Created Apr 13, 2026
Stars 0 Forks 0 Watchers 0 Open issues 0 Open PRs 0
History

4 branches 3 tags

main Ready for production 8cd5464
Delete 4_Schematics and Boards Layout/4_6_Schematics/MainBoard/RADAR_… 2bd5290
Final touch (added via fencing and stop mask to ADTR1107 CPLR traces 4b441a2
Merge pull request #46 from NawfalMotii79/develop c8fa961
fix: remove server credentials from constraints README e4db996
docs: update constraints README with USB_MODE architecture and build … 75854a3
refactor(host): remove FT601 references from radar_dashboard, smoke_t… 7c82d20
test: update test_radar_dashboard for FT2232H-only protocol c1d12c4
refactor(host): remove FT601 support from radar_protocol.py 385a54d
Add files via upload f1126d6
Merge pull request #45 from JJassonn69/feat/usb2.0-support 4255eff
fix: add explicit reset for status_words to suppress Synth 8-7137 war… 274abd7
feat(usb): add FT2232H USB 2.0 interface for 50T production board 408f4d1
Merge remote-tracking branch 'origin/main' into develop 3e737fb
Add files via upload 0db0e7b
fix(xdc): add hold false_path for ADC IDDR + reorganize build scripts… 849b322
fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butt… 8d7b6e0
fix(rtl): add DONT_TOUCH attribute to prevent opt_design from gutting… d1927f1
feat(rtl): add radar_system_top_50t wrapper to solve IO pin overflow a0469cf
fix(scripts): disconnect nets before removing unconstrained ports 802dca2
fix(scripts): switch 50T build to non-project-mode impl + remove unco… 23eb88c
fix(constraints): change adc_pwdn from LVCMOS33 to LVCMOS25 for Bank … 44460e7
fix(scripts): inject DRC waivers via TCL.PRE hook for impl_1 child pr… 96856c4
fix(constraints,scripts): resolve 50T build failures — LVDS_25 + DRC … 7d90e5e
fix(constraints): use LVDS (not LVDS_33) for 50T Bank 14 ADC inputs 30f56f3
fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-t… d50e51a
fix(scripts,constraints): handle empty STATS properties in build summ… 1f315a6
fix(scripts): fix TCL command substitution and impl status race in al… 6657e11
fix(test,docs): remove dead xfft_32 files, update test infra for dual… 1e28476
Merge pull request #41 from joyshmitz/fix/tcl-portability 04982a3
Merge pull request #42 from joyshmitz/fix/dual-subframe-consistency 9b383fc
fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT… ffc89f0
fix(scripts): make Vivado TCL scripts portable and update RTL file lists 48b3847
Merge pull request #40 from joyshmitz/docs/readme-contributing 22758fa
docs: fix FPGA part number, dead paths, and add CONTRIBUTING.md 7eb8166
Add files via upload 73d6d9b
Delete 4_Schematics and Boards Layout/4_7_Production Files directory 0f5a04f
Add files via upload 8e0a90f
Delete docs/assets/img/Nawfal.png 10e0914
Revise index.html for AERIS-10 documentation site 168b9b2
Update image links to use raw GitHub URLs a343c85
Revise README for clarity and image updates 7ffd1f6
Add files via upload f12405e
Add files via upload 7241100
Revise index.html with new images and metadata 1beb7dc
Add files via upload 49e22b8
Add files via upload c7fa099
Delete 8_Utils directory 81bf4ca
Fix image paths in README.md cfbe6d2
Refactor index.html for improved layout and SEO e4fa118
Delete index.html c91e4b4
Add files via upload b7f4044
Update index.html for absolute paths and styles 2ec636e
Add initial HTML structure for AERIS-10 project a6205bd
Delete index.html bbd0556
Add index.html for AERIS-10 documentation 8668112
Add files via upload d8d1d34
Delete 4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/Power… 484bf09
Fix badge syntax in README.md f5d89fd
Fix image formatting in README.md a3d0d3f
Merge pull request #33 from JJassonn69/fix/staggered-prf-dual16-doppler 46c37e1
Fix staggered-PRF Doppler processing with dual 16-point FFTs a577b76
Add sponsors section to README 2a89713
Add files via upload f5765f6
Delete 14_RADAR_Old_version directory 02eb0b9
Merge pull request #30 from JJassonn69/main 93c75d1
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean) 5499827
add TE0713 heartbeat bring-up artifact 9dee28a
GUI: add self-test UI, fix opcode mismatches (0x16->0x06, 0x04->0x05)… f9ad30e
Wire self-test results (0x31) to USB status readback path, add fpga_s… 4985ecc
Fix 5 GUI bugs: threaded connect, button toggle, live CFAR/MTI/DC rep… eb907de
Add radar dashboard GUI with replay mode for real ADI CN0566 data vis… f8d80cc
Full-chain MTI+CFAR real-data co-simulation: bit-exact match across a… 7a44f19
Build 25 engineering report: MTI canceller + DC notch timing PASS d5d28e9
Integrate MTI canceller and DC notch filter for ground clutter removal ed629e7
Change radar system image format to PNG eb8e063
Replace radar system image with updated version 4801cb8
Add Build 24 15-point engineering report: timing, utilization, DSP/BR… 075ae1e
Added Full Diagram 0b170f7
Complete Diagram d7fc8c6
Pipeline CFAR noise computation: break critical path for timing closure 0745cc4
Integrate CA-CFAR detector: replace fixed-threshold comparator with a… f71923b
Production fixes 1-7: detection bugs, cfar→threshold rename, digital … e93bc33
Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048… 0b06436
Added Full Diagram b01c507
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21 19284ac
Complete Diagram 836bf8f
Fix Vivado DRC: consolidate data_pending flags into single always blo… 2efab23
Add Build 21 TCL script for FFT opts + E2E RTL fixes Vivado build 05efe69
Update docs for FFT optimizations + E2E test + RTL fixes (19/19 FPGA … a31b4ec
E2E integration test + RTL fixes: mixer sequencing, USB data-pending … 0773001
FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughp… a3e1996
Update docs for Gap 2 GUI Settings completion (5 of 7 gaps closed) 02b3b68
Gap 2 GUI Settings: runtime chirp timing, stream control gating, stat… 7cdfa48
Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 s… d2f20f5
Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, … e5d1b3c
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix c6103b3
Gap 3 Safety Architecture: IWDG watchdog, Emergency_Stop PA rail cuto… f3bbf77
Fix chirp memory loader BRAM async reset (Gap 5, REQP-1839/1840) c87dce0
Add Phase 0 Vivado-style lint to regression runner, update golden data 94ffdb8